In printed circuit board (PCB) and integrated circuit (IC) substrate manufacturing it is required that electronic components are bonded to selected bonding areas (bond pads as the bonding portion) of a copper structure produced on one or on both sides of the substrate. Such interconnection must be reliable in terms of bond strength, i.e., thermal stress imposed on a bonding interconnection must by no means result in a break of this interconnection.
Wire bonding is one of the preferred processes for connecting the chip to the IC-substrate in IC packages and it accounts for more than 70% of the commercial IC production. Currently the main wire bonding process used for IC-substrate is gold wire bonding, wherein a gold wire is bonded on a layer of electrolytically deposited nickel and gold. Alternatively, the gold wire is bonded onto a surface of nickel, palladium and gold (ENEPIG). In all cases, the copper wire is bonded onto the final gold layer. Recently, copper wire bonding technology has been introduced into the IC-substrate Industry as an alternative to gold wire bonding. Currently the standard for copper wire bonding is to use copper wire bonds bonded onto a layer sequence consisting of a first electrolytic nickel and second gold layer deposited onto the copper wire bonding portions of the substrate.
The mechanical reliability of wire bonds in microelectronic package depends to a big extent on the formation and development of intermetallic compounds at the interface between the bond wedge and the bond pad on the substrate (printed circuit board, PCB or IC-substrate), which is strictly needed for successful bonding.
Bonding either gold or copper-wires onto a copper bond pad surface is difficult mainly because of the high tendency of the copper metallization to oxidise.
Wire bonding portions are typically made of copper. If they remain bare or are externally exposed to atmosphere and humidity, soldering and wire bonding properties of the copper layers deteriorate due to oxidation or corrosion of the surface. In order to maintain soldering or wire bonding properties, therefore, the bare or exposed copper layers are usually electroplated or electroless plated with nickel. The plated nickel layer protects the copper from an erosive atmosphere for a long period of time. Also, the nickel layer protects the copper from being dissolved by solder during the soldering assembly step by functioning as a diffusion barrier layer. In addition, the plated nickel layer plays a role as an interfacial film for preventing the copper layer and the gold layer, to be plated later, from diffusing into each other. Thereafter, wire bonding gold is plated to a thickness of around 0.5 μm in an electrolytic or electroless manner, so as to impart properties facilitating a wire bonding process. Such processes are for example described in U.S. Pat. No. 5,235,139 and U.S. Pat. No. 6,733,823. US 2007/0104929 relates to a method for plating a printed circuit board, comprising the steps of: (a) providing a printed circuit board with predetermined circuit patterns, having a wire bonding portion for surface mounting semiconductors thereon and a soldering portion for connecting external parts with the printed circuit board; (b) forming a photo solder resist layer to the remaining portions exclusive of the wire bonding portion and the soldering portion in the printed circuit board; (c) forming an electroless palladium or palladium alloy plated layer on the wire bonding portion and the soldering portion; and (d) immersing the palladium or palladium alloy plated layer with a substitution type immersion gold plating solution containing a water-soluble gold compound to form an electroless gold or gold alloy plated layer on the palladium or palladium alloy plated layer.
US 2006/055023 concerns a chip carrier comprising a laminated layer and an oxidation protection layer. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by deploying a simple, fast film-coating technique.
U.S. Pat. No. 5,175,609 relates to new structures and methods for corrosion- and stress-resistant interconnecting multilayer metallurgical pad comprising sequentially deposited layers of chromium, nickel and noble or relatively noble metal as the interconnecting metallurgy, or multilayer metallurgical pad comprising sequentially deposited layers of chromium, soluble noble metal, nickel and noble or relatively noble metal as the interconnecting metallurgy.
EP 0 697 805 A1 relates to a way of manufacturing printed circuit boards by providing a circuit board with a circuit pattern, holes and lands of copper; covering the circuit pattern with a soldermask; and contacting the board with an electroless palladium solution for a sufficient time to provide a final finish layer of palladium at a sufficient thickness to protect the copper deposits in the holes and on the lands from oxide formation and being relatively smooth and flat to provide good solderability and good wire bonding capabilities. The copper circuit pattern, holes and lands is generally provided by plating copper onto the board. Then, the palladium layer may be provided directly onto the copper or onto a layer of electroless nickel which is initially deposited upon the copper.